1. Field
The present disclosure pertains to the field of information processing, and more specifically, to the field of data error correction within a memory, such as cache memory.
2. Background
Computer systems and/or microprocessors may use one or more cache memories to provide relatively fast access to recently used data. FIG. 1, for example, shows a computer system consisting of a processor, cache, and memory. In general, the cache module may consist of multiple levels of cache, however, for simplicity only one level of cache is shown. When the processor fetches instructions or data (generically referred to as “data”), it may first access the cache module. If the access results in a cache “hit” (i.e., the requested data is present in the cache), the cache may supply the data to the processor. If the access results in a miss (i.e., the requested data is not present in the cache), the cache may access the corresponding line from the memory (e.g., DRAM) and then store it in the cache.
In the case that a processor programs, or “writes”, data to memory (via issuing a “write request” transaction to from the processor to the memory, for example), the data may or may not be written directly to the memory, depending on the write policy of the cache. For example, if the cache uses a “write-through” policy, the data may be written to the cache as well as the memory. Whereas, if the cache uses a “write-back” policy, data may be written only to the cache and the corresponding cache line may be marked as “modified” and then written back to memory when the line is evicted from the cache.
The choice of whether to use a write-back cache or a write-through cache depends upon several design concerns, such as available bus bandwidth. In general, a write-back cache may require less bus bandwidth than a write-through cache. In order to conserve off-chip bus bandwidth (i.e., bus bandwidth from the processor to memory), many modern cache hierarchies may use a write-back policy.
A cache memory may be susceptible to data corruption, causing erroneous data to be stored in the cache and used by a processor. Erroneous data in the cache, if not detected, can result in a processor using the erroneous data to enter an undesired state and/or generate an undesired result. Cache errors, or “faults”, that are detected but cannot be corrected, are sometimes referred to as detected unrecoverable errors (DUE).
For write-through caches (i.e., those caches using a write-through policy), a copy of all cached data is available in memory. Therefore, write-through caches may be protected from cache faults by merely detecting the cache error, via error detection codes (EDC), for example, which may be used in a parity check against the cache data. In a write-through cache, if an error is detected in a cache line, the corresponding cache line may be invalidated and a copy of the line read from memory.
However, for write-back caches, copies of the modified cache lines are not necessarily available in a memory system. If write-back caches are protected only with EDC, then an error in a modified line can result in a DUE condition. To avoid a DUE condition, write-back caches typically use error correction codes (ECC), which are used not only to detect but also to correct the cache fault.
FIG. 2 illustrates a prior art four-way set associative cache array, in which each line (lines 0, 1, 2, 3) has a corresponding ECC (ECC 0, 1, 2, 3). In the example of FIG. 2, each line contains information to indicate whether the line is valid (“vld” field), whether the line has been modified (“mod” field), and whether the line is to be replaced, or “evicted”, (“repl” field). Furthermore, each line contains an indicate of what memory address the line corresponds to (“tag” field), and the data/instruction stored in the cache line (“data” field).
Because each cache line has a corresponding ECC, the prior art cache array of FIG. 2 may require substantial storage overhead. ECC storage overhead is increased if a cache uses a uniform fault-tolerance policy for all the cache lines, and therefore includes an ECC for each cache line. Accordingly, processors and/or computing systems containing write-back caches that use ECC may incur substantial cost in area and power consumption over those that use write-through caches. Therefore, the full bus throughput benefits of write-back cache systems may be needlessly offset by additional hardware overhead for various computer systems and processors.